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M34D64
64 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory
FEATURES SUMMARY 2 s Two Wire I C Serial Interface Supports 400 kHz Protocol
s
Figure 1. Packages
Single Supply Voltage: - 2.5V to 5.5V for M34D64-W - 1.8V to 5.5V for M34D64-R
s
Hardware Write Control of the top quarter of memory BYTE and PAGE WRITE (up to 32 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1M Erase/Write Cycles More than 40 Year Data Retention
8 1
SO8 (MN) 150 mil width
s s s s s s s
TSSOP8 (DW) 169 mil width
April 2003
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M34D64
SUMMARY DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8. Figure 2. Logic Diagram
SCL Serial Clock Write Control Supply Voltage Ground
Table 1. Signal Names
E0, E1, E2 SDA Chip Enable Serial Data
VCC
WC VCC
3 E0-E2 M34D64 SCL WC SDA
VSS
VSS
AI02850B
Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal.
These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 3. SO and TSSOP Connections
M34D64 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02851C
VCC WC SCL SDA
Note: 1. See page 17 (onwards) for package dimensions, and how to identify pin-1.
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SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V CC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or VSS, to establish the Device Select Code. Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the top quarter of the memory (as shown in Figure 4) from inadvertent erase or write. The Write Control signal is used to enable
(WC=VIL) or disable (WC=VIH) write instructions to the top quarter of the memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed.
Figure 4. Memory Map showing Write Control Area
1FFFh Write Controlled Area 1800h
1000h
0800h
0000h
AI03114C
Figure 5. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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Figure 6. I2C Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
Table 2. Device Select Code
Device Type Identifier1 b7 Device Select Code 1 b6 0 b5 1 b4 0 Chip Enable Address2 b3 E2 b2 E1 b1 E0 RW b0 RW
Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 4. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
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DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M34D64 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Table 5. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = 0
32
START, Device Select, RW = 0
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Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC ACK BYTE WRITE DEV SEL ACK ACK DATA IN ACK
BYTE ADDR R/W
BYTE ADDR
WC ACK PAGE WRITE DEV SEL ACK ACK DATA IN 1 ACK DATA IN 2
START
BYTE ADDR R/W
BYTE ADDR
WC (cont'd)
START
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
STOP
AI01106C
Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte(s). Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the contents of the top quarter of the memory. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by the Least Significant Byte (Table 4). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Byte Write After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected (top quarter of the memory), by Write Control (WC) being driven High, the location is not modified. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Page Write The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as
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data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 32 bytes of data. If Write Control (WC) is High, the contents of the addressed top quarter of the memory location are Figure 8. Write Cycle Polling Flowchart using ACK not modified. After each byte is transferred, the internal byte address counter (the 5 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Tables 13 and 14, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 8, is: - Initial condition: a Write cycle is in progress.
- Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
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M34D64
Figure 9. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
NO ACK DATA OUT STOP ACK
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL *
ACK
ACK DEV SEL * START
ACK
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 4th bytes) must be identical.
Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. Random Address Read A dummy Write is performed to load the address into the address counter (as shown in Figure 9) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 9, without acknowledging the byte.
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Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode.
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M34D64
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 6. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 SO: 20 seconds (max) 1 TSSOP: 20 seconds (max) 1 -0.6 -0.3 -4000 Parameter Min. -65 Max. 150 235 235 6.5 6.5 4000 Unit C C V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M34D64
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 7. Operating Conditions (M34D64-W)
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 8. Operating Conditions (M34D64-R)
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
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M34D64
Table 9. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 10. AC Measurement I/O Waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 10. Input Parameters
Symbol CIN CIN ZWCL ZWCH tNS Parameter1,2 Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.5 V VIN > 0.7VCC Single glitch 50 500 100 Test Condition Min. Max. 8 6 300 Unit pF pF k k ns
Note: 1. TA = 25 C, f = 400 kHz 2. Sampled only, not 100% tested.
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M34D64
Table 11. DC Characteristics (M34D64-W)
Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (E2, E1, E0, SCL, SDA) Input Low Voltage (WC) VIH VOL Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V Test Condition (in addition to those in Table 7) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , VCC = 2.5 V -0.3 -0.3 0.7VCC Min. Max. 2 2 1 10 2 0.3VCC 0.5 VCC+1 0.4 Unit A A mA A A V V V V
VIL
Table 12. DC Characteristics (M34D64-R)
Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (E2, E1, E0, SCL, SDA) Input Low Voltage (WC) VIH VOL Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V Test Condition (in addition to those in Table 8) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =1.8V, fc=100kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 1.8 V - 0.3 -0.3 0.7VCC Min. Max. 2 2 0.8 0.2 0.3 VCC 0.5 VCC+1 0.2 Unit A A mA A V V V V
VIL
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M34D64
Table 13. AC Characteristics (M34D64-W)
Test conditions specified in Table 9 and Table 7 Symbol fC tCHCL tCLCH tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW
Note: 1. 2. 3. 4.
Alt. fSCL tHIGH tLOW tR tF tR tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency
Parameter
Min.
Max. 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time
600 1300 300 300 20 20 100 0 200 200 600 600 600 1300 5 or4 10 900 300 300
ns ns ns ns ns ns ns ns ns ns ns ns ms
For a reSTART condition, or following a Write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. The Write Time of 5 ms only applies to devices bearing the process identification letter "B" in the package marking (on the t op side of the pack-age), otherwise (for devices bearing the process identification letter "N") the Write Time is 10 ms. For further de tails, please contact your nearest ST sales office.
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M34D64
Table 14. AC Characteristics (M34D64-R)
Test conditions specified in Table 9 and Table 8 Symbol fC tCHCL tCLCH tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency Clock Pulse Width High Clock Pulse Width Low SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time 600 1300 20 100 0 200 200 600 600 600 1300 10 900 300 Parameter Min. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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M34D64
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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M34D64
PACKAGE MECHANICAL SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M34D64
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Notes: 1. Drawing is not to scale.
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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PART NUMBERING Table 15. Ordering Information Scheme
Example: Device Type M34 = I2C Application Specific Standard Product serial access EEPROM Device Function 64 = 64 Kbit (8192 x 8) Operating Voltage W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) Temperature Range 6 = -40 to 85 C Option T = Tape & Reel Packing M34D64 - W MN 6 T
Devices are shipped from the factory with the memory content set at all 1s (FFh).
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M34D64
REVISION HISTORY Table 16. Document Revision History
Date 23-Mar-1999 09-Jun-1999 16-Nov-2000 13-Sep-2002 04-Apr-2003 Rev. 1.0 1.1 1.2 2.0 2.1 Document written Memory Map illustration added. Line removed from Tab-2 M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to 3.6V ranges removed; 0 to 70C and -20 to 85C ranges removed New edition. TSSOP8 package added Addresses on Memory Map figure corrected. tW of 5ms offered on certain versions of the device (bearing process identification letter "B") Description of Revision
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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